INSTRUCTION SET ARCHITECTURE AS A LEVER FOR BETTER SECURITY, PERFORMANCE AND EFFICIENCY IN GENERAL PURPOSE PROCESSORS
In general purpose processors, the instruction set architecture changes little over time, to maximize software compatibility. In this talk, I make the case that abandoning that approach can provide big gains in performance, efficiency, and security without actually impacting software compatibility. I will discuss a couple of different ways to do this, potentially changing the ISA at the millisecond, microsecond, or even cycle granularity. The first is heterogeneous-ISA multicore architectures, where threads freely move between cores that run completely different ISAs, taking better advantage of diversity in the instruction stream than previous single-ISA heterogeneous architectures. I will also discuss contextsensitive decoding, which leverages the external ISA to micro-op (internal ISA) translation that happens in the decoder. By making that previously static translation dynamic, possibly changing every few cycles, we can instantly transform the instruction stream to change security levels, add performance features, etc.