Curriculum Vitae

Dr. Sheldon X.-D. Tan

Associate  Professor

Engineering Build Unit-2, Rm424

Department of Electrical Engineering,

University of California at Riverside,

Riverside, CA 92521.

Tel: (951)-827-5143;  Fax: (951)-827-2425

Email: stan@ee.ucr.edu

Web: http://www.ee.ucr.edu/~stan

Education      

  • Ph.D.  in Electrical and Computer Engineering,  University of Iowa, Iowa City, IA, 1996-1999

Advisor: Prof. Richard Shi at University of Washington.

 

  • M.Sc. in Electrical Engineering, Fudan University, Shanghai, P.R. China, 1992-1995

           

  • B.S. in Electrical Engineering, Fudan University, Shanghai, P.R. China, 1988-1992

Publication List

Awards and Honors

·         Best Paper Award, IEEE Int. Conf. on Computer Design (ICCD), Lake Tahoe, CA, 2007

·         Best Paper Award Nomination,  42th IEEE/ACM Design Automation Conference, Anaheim, CA, 2005

·         National Science Foundation CAREER Award, 2004.

·         UC Regent’s Faculty Fellowship, 04-05, 06-07.

·         Best Paper Award, 36th IEEE/ACM Design Automation Conference,  New Orleans, LA, 1999.

·         First Place Poster Award (Ph.D. Dissertation), The Annual Conference of the NSF Center for Design of Analog-Digital Integrated Circuits (CDADIC), Seattle, WA, 1999.

·         Listed in Who’s Who in Engineering Education (AcademicKey), 2005 –

·         Listed in Who’s Who in Science and Engineering (Marquis), 2007 -

·         GuangHua Fellowship (sponsored by GuangHua Foundation), Fudan University 1993.

·         Best Graduate Student Award, Fudan University 1992.

·         Best College Student Award, Shanghai, China 1991.

·         Outstanding College Students (Renming) Scholarships, Fudan University, 1988-1992.

Research and Employment Experience

·         Associate Professor, University of California at Riverside, Riverside, CA. 07/2006 – present

·         Guest Professor, Fudan University, Shanghai, China, 03/08 - present

·         Assistant Professor, University of California at Riverside, Riverside, CA. 07/2002 – 06/2006.

·         Member of Technical Staffs,  Altera Corporation, San Jose, CA.  01/01 – 007/02.

·         Member of Technical Staffs,  Monterey Design Systems, Sunnyvale, CA. 08/99 --01/01.

·         Visiting Research Assistant, University of Washington, Seattle, WA. 09/98 – 05/99.

·         Summer Intern, Avant! Corp. (now Synposys), Fremont, CA. 05/98 – 09/99.

·         Summer Intern, Rockwell Semiconductor Systems, Newport Beach, CA. 07/97 – 09/97.

·         Research Assistant,  University of Iowa, IA. 09/96 – 09/98.

·         Member of Faculty,  Fudan University, Shanghai, China. 07/95 – 08/96.

Professional Activities

 

Editorial Board

 

 

Technical Program Committee Members

·         IEEE Southwest Symposium on Mixed-Signal Design (SSMSD)

2003

·         IEEE International Symposium on Circuits and Systems (ISCAS)

2004, 2005, 2006, 2007, 2008.

·         IEEE/ACM Asia and South Pacific-Design Automation Conference (ASPDAC), 

2005 (subcommittee chair) , 2006, 2007

·         IEEE International Behavioral Modeling and Simulation Conference (BMAS),

2005, 2006

·         IEEE International Symposium on Quality Electronic Design, (ISQED),

2006, 2007, 2008

·         IEEE International Conference on Computer-Aided Design (ICCAD),

2006, 2007

 

Conference Session Chairs

·         Session co-chair for Asia Pacific-Design Automation Conference (ASPDAC) 2000.

·         Session co-chair for IEEE International Symposium on Circuits and Systems (ISCAS), 2002.

·         Session co-chair for IEEE International SoC Conference (SOC), 2003

·         Session chair for IEEE International Symposium on Circuits and Systems (ISCAS), 2004.

·         Session chair for Asian South Pacific Design Automation Conference (ASPDAC),

2005, 2006, 2007, 2008

·         Session chair for Asian South Pacific Design Automation Conference (ASPDAC), 2006.

·         Session chair for IEEE International Symposium on Quality Electronic Design, (ISQED),

2006, 2007.

·         Session chair for IEEE International Behavioral Modeling and Simulation Conference (BMAS), 2006

·         Session chair for IEEE International Conference on Computer-Aided Design (ICCAD),

2006, 2007

 

Invited Presentations:

·         Cadence Design Systems, Inc. San Jose, CA,  “Efficient Area Optimization of VLSI Power/Ground (P/G) networks”, July 16, 2002

·         Fudan Univ. Shanghai, China, “Area Optimization of VLSI Power/Ground Networks”, Jan. 21, 2003.

·         University of California at San Diego, Department of Electrical and Computer Engineering, San Diego, CA, “Symbolic Analysis of Analog Circuits with Determinant Decision Diagrams”, Feb. 4, 2003.

·         Fujitsu American Research Lab,  Sunnyvale, CA, “Modeling and Simulation for Mixed-Signal System-On-a-Chip Designs”, Aug. 21, 2003.

·         The 5th International Conference on ASIC, Beijing, China,  “Circuit level alternating-direction-implicit approach to transient analysis of power distribution networks”, Oct, 21, 2003.

·         Tsinghua University, Beijing, China, “Fast power/ground network analysis and optimization”, Oct. 2003.  

·         Cadence Design Systems Inc., San Jose, CA, “Robust VLSI  Power Delivery, a Verification perspective”,  May 05, 2004.

·         Cadence Design Systems Inc., San Jose, CA, “Efficient Decap Budgeting Algorithm for Large On-Chip Power Delivery Networks”, Oct. 10, 2004.

·         Synposys Corporation Inc., San Jose, CA, “A General MIMO Linear Network Reduction and Realization”, Oct. 11, 2004.

2005

·         International on System-on-a-chip Workshop (ICSOC’05), Chengdu, China, “Efficient Decap Budgeting and Optimization”, Aug. 16, 2005.

·         Tsinghua University, Beijing, China, “Modeling and Simulation of Nanometer Interconnect Circuits”, Aug. 23, 2005.

·         Cadence Design Systems, Inc., San Jose, CA, “Passive model order reduction and terminal reduction for interconnect circuits with multiple terminals”, Nov. 9, 2005.

·         Tessera Technologies Inc. Inc. San Jose, CA, “Thermal issues in packaging design and fast packaging-level thermal analysis”, Oct. 10, 2005.

2006

·         University of Tokyo, Tokyo, Japan, “Hierarchical model order reduction for wideband interconnect modeling”, Jan. 25, 2006.

·         Cadence Design Systems, Inc., San Jose, CA, “TermMerg: Fast terminal reduction for interconnect circuits with multiple terminals”, Feb. 7, 2006.  

·         Cadence Design Systems, Inc., San Jose, CA, “An extended SVD-based terminal and model order reduction algorithm”, June 12, 2006.  

·         Tsinghua University, Beijing, China, “Statistical On-Chip Power Delivery Network Analysys ”, Aug. 22, 2006.

·         System LSI Design Workshop, Fukuoka, Japan, “Recent Advance in Terminal and Model Order Reduction for Interconnect Circuits”, Sept. 9, 2006.

2007

·         Electrical Engineering Colloquium, UCR, “Modeling and Simulation of  Sub-90nm Interconnect Circuits: Problem, Solution and Future Challenges”, May 7, 2007.

·         Computer Science and Engineering Colloquium, UCR, “Architecture-level thermal and power modeling and simulation for high performance microprocessor”, May 21, 2007.

·         Beijing JiaoTong University, Beijing, China, “Modeling and analysis of 90nm VLSI Interconnects: problem, solutions and future challenges”, July 5, 2007.

·         Bejing Normal University, Beijing, China,” Architecture-level power modeling and thermal estimation for high performance microprocessor designs”, July 9, 2007.

·         Tsinghua University, Beijing, China, “Architecture-level pow