Publication List for MSLAB (1994-present)Please be aware that all papers are copyrighted by the organizations responsible for the corresponding conferences or journals.
We would like to thank National Science Foundation (NSF) and other funding agencies for their generous supports for the research works and the corresponding publications from MSLAB.
Any opinions, findings, and conclusions or recommendations expressed in those materials below are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
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Books
B1. Zhanhai Qin, Sheldon X.-D. Tan and Chung-Kuan Cheng, Symbolic Analysis and Reduction of VLSI Circuits, Springer Publisher, 2005, ISBN: 0-387-23904-9; e-ISBN: 0-387-23905-7.
B2. Sheldon X.-D. Tan and Lei He, Advanced Model Order Reduction Techniques for VLSI Designs, Cambridge University Press, 2007, ISBN-13 978-0-521-86581-4, ISBN-10 0-521-86581. |
Book Chapters:
B3. C.-J. Shi and X.-D. Tan, “Canonical Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams” Part III and pp.344-361 in Computer-Aided Design of Analog Integrated Circuit and Systems, R. A. Rutenbar, G. E. Gielen and B. A. Antao (ed) , IEEE Press & Wiley-Interscience, 2002. ISBN 0-471-22782-X.
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Tutorials:
T1. Paul M. Harvey, Howard Chen, Chung-Kuan Cheng, Manjid Borah, Lei He, and Sheldon X.-D. Tan, "High Performance Interconnect and Packaging", full day tutorial, IEEE/ACM Asia South-Pacific Design Automation Conference, January 24, 2006.
T2. Sheldon X.-D. Tan, Jeffrey Fan, “Inductance Extraction and Compact Modeling of Inductively Coupled Interconnects in the Presence of Process Variations”, half-day tutorial, ASICON’07, Oct. 2007 (invited). |
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Patents:
P1. Sheldon X.-D. Tan, X. Wang, B.A. Fairbanks, “I/O Pin Placement Algorithm For Programmable Logic Devices” Filed on May, 2003. U.S. Patent No. 7111265 (approved on 9/19/2006).
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Journal Articles
J1. X.-D. Tan, J.-R. Tong, and P.-S. Tang. “A general algorithm for multi-way digital circuit partitioning.” Journal of Electronics, vol. 24, no. 8, 1996. J2. X.-D. Tan, J.-R. Tong, and P.-S. Tang. “A multiple-optimization algorithm for multiple way VLSI network partitioning,” Chinese Journal of Computers , vol. 19, no. 5, 1996. J3. C.-J. Shi and X.-D. Tan. “Canonical symbolic analysis of large analog circuits with determinant decision diagrams.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 1, pp. 1-18, 2000. J4. X.-D. Tan and C.-J. Shi. “Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, pp. 401-412, 2000. J5. C.-J. Shi and X.-D. Tan. “Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 813-827, 2001. J6. S. X.-D. Tan and C.-J. Shi. “Efficient vary large scale integration power/ground network sizing based on equivalent circuit modeling.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 3, pp.277-284, 2003. J7. X.-D. Tan and C.-J. Shi. “Balanced multi-level multi-way partitioning of large analog integrated circuits for hierarchical symbolic analysis.” Integration, The VLSI Journal, vol 34/1-2 pp 65 – 86, 2003. J8. X.-D. Tan, C.-J. Shi and F. J.-C. Lee. “Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. vol. 22, no. 12, pp. 1678-1684, Dec. 2003. J9. S. X.-D. Tan and C-J. Shi. “Efficient DDD-based interpretable symbolic characterization of large analog circuits”, IEICE Transactions on Fundamentals, pp.3112-3118, vol. E86-A, No.12, Dec. 2003. J10. S. X.-D. Tan and C-J. Shi, “Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No.6, pp. 907-918, June 2004. J11. W. Guo, S. X-.D. Tan, Z. Luo, X. Hong, “Partial random walks for transient analysis of large power distribution networks”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E87-A, No. 12 pp. 3265-3272, December 2004. J12. J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan and Z. Pan, “A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E87-A, No. 12 pp.3273-3280, December 2004. J13. S. X.-D. Tan, “A general hierarchical circuit modeling and simulation algorithm”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 418-434, March 2005. J14. X.-D. S. Tan, W. Guo and Z. Qi, “Hierarchical approach to exact symbolic analysis of large analog circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 8, pp. 1241-1250, 2005. J15. Y. Zou, Y. Cai, Q. Zhou, X. Hong, S. X.-D. Tan, “A fast delay computation for the hybrid structured clock networks”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, Vol.E88-A No.7 pp.1964-1970, July 2005. J16. Z. Qi,, H. Yu, P. Liu, S. X.-D. Tan, L. He, “Wideband passive multi-port model order reduction and realization of RLCM circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol. 25, No. 8, pp. 1496-1509, Aug. 2006. J17. J. Yang, S. X-D. Tan, “Nonlinear transient and distortion analysis via frequency-domain Volterra series”, Journal of Circuits, Systems & Signal Process, vol. 25, No. 3, pp.295-314, 2006. J18. H. Li, J. Fan, Z. Qi, S. X-D. Tan, L. Wu, Y. Cai, X. Hong, “Partitioning-based approach to fast on-chip decap budgeting and minimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp.2402-2412, Nov. 2006. J19. P. Liu, H. Li, L. Jin, W. Wu, S. X.-D. Tan and J. Yang, “Fast thermal simulation for runtime temperature tracking and management”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 25, no. 12, pp. 2882-2893, 2006. J20. Y. Cai, J. Fu, X. Hong, S. X-D. Tan, Y. Luo, “Power/ground network optimization considering decap leakage currents”, IEEE Transaction on Circuit and System II, vol. 53, no. 10, pp.1012-1016, Oct. 2006. J21. S. X-D. Tan, “Symbolic analysis of analog circuits by Boolean logic operations”, IEEE Trans. Circuit and Systems-II, vol. 53, no. 11, pp.1313-1317, Nov. 2006. J22. J. Fan, S. X-.D. Tan, Y. Cai and X. Hong, “Partitioning-based decap capacitor budgeting via sequence of linear programming”, Integration, The VLSI Journal, vol. 40, no.4, pp. 516-524, 2007. J23. P. Liu, S. X.-D. Tan, J. Kong, B. McGaughy, L. He, “TermMerg An efficient terminal reduction method for interconnect circuits considering delay variations” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp1382-1392, 2007. J24. Y. Cai, Z. Pan, S. X.-D. Tan, X. Hong, J. Fu, “Fast analysis of power/ground networks via circuit reduction”, Chinese Journal of Semiconductors, vol. 26, no. 7, pp.1340-1345, 2005. J25. J. Shi, Y. Cai, J. Fan, S. X.-D. Tan and X. Hong, “Pattern based method for extreme large power/ground analysis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp.680-692, April 2007. J26. W. Wu, L. Jin, , J. Yang, P. Liu and S. X.-D. Tan, “Efficient power modeling and software thermal sensing for runtime temperature monitoring ”, ACM Transaction on Design Automation of Electronic Systems (TODAES), vol. 12, no. 3, August, 2007. J27. B. Liu, S. X.-D. Tan, “Minimum decoupling capacitor insertion in VLSI power/ground supply networks by semidefinite and linear programs”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 15, no. 11, pp. 1284-1287, Nov. 2007 J28. Z. Luo, Y. Cai, S. X.-D. Tan, X. Hong, Y. Wang, Z. Pan, J. Fu, “Time-domain analysis methodology for large-scale RLC circuits and its applications”, Science in China F Series, vol. 49, no. 5, pp. 665-680, Oct., 2006. J29. P. Liu, S. X.-D. Tan, B. Yan, B. McGaughy, “An efficient terminal and model order reduction algorithm”, Integration, the VLSI Journal, vol.41, no.2, pp.210-218, Feb. 2008. (online permanent DOI link) J30. Y. Cai, L. Kang, J. Shi and X. Hong and S. X.-D. Tan, “Random walk guided decap embedding for power/ground network optimization”, IEEE Trans. Circuit and Systems-II (TCAS-II), vol. 55, no. 1, pp.36-40, Jan. 2008. J31. Y. Cai, J. Shi, Z. Pan, X. Hong and S. X.-D. Tan, “Large scale P/G grid transient simulation using hierarchical relaxed approach”, Integration, the VLSI Journal, vol.41, no.1, pp.153-160, Jan. 2008. J32. N. Mi, J. Fan, S. X.-D. Tan, Y. Cai and X. Hong, “Statistical analysis of on-chip power delivery networks considering lognormal leakage current variations with spatial correlations”, IEEE Transaction on Circuit and System I (TCAS-I), (in press). J33. B. Yan, S. X.-D. Tan, B. McGaughy, “Second-order balanced truncation for passive order reduction of RLCK circuits”, IEEE Transaction on Circuit and System II (TCAS-II), (in press). J34. N. Mi, B. Yan, S. X.-D. Tan, “Multiple block structure-preserving reduced order modeling of interconnect circuits” Integration, The VLSI Journal (in press). (online permanent DOI link) J35. S. X.-D. Tan, P. Liu, L. Jiang, W. Wu, M. Tirumala, “A fast architecture-level thermal analysis method for runtime thermal regulation”, ASP Journal of Low Power Electronics (JOLPE), (in press) J36. N. Mi, S. X.-D. Tan, Y. Cai and X. Hong, “Fast variational analysis of on-chip power grids by stochastic extended Krylov subspace method”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (in press). J37. D. Li, S. X.-D. Tan, L. Wu, “Hierarchical Krylov subspace based reduction of large interconnects”, Integration, The VLSI Journal (in press). J38. D. Li, S. X.-D. Tan, E. H. Pacheco, M. Tirumala, “Architecture-level thermal characterization for multi-core microprocessors”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), (in press). Journal Articles (Submitted and Revised)J39. W. Wu, J. Yang, S. X.-D. Tan, S.-L. Lu, “Reliability-enhanced on-chip data caches considering process variations”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), (submitted). J40. B. Liu, S. X.-D. Tan and A. Kahng, “Scalable frequency analysis of nanometer VLSI system power delivery networks via stochastic moment matching”, IEEE Transaction on Circuit and System I (revised). J41. H. Yu, D. Smart, C. Chu, Y. Shi, L. He and S. X.-D. Tan, “Block structure preserved macromodeling for large scale inductive interconnect”, IEEE Transaction on Circuit and System I (submitted). J42. J. Fan, N. Mi, S. X-D Tan, W. Zhao, Y. Cai, X. Hong, “Variational reduced order modeling of interconnect circuits by spectral stochastic method", Journal of Analog Integrated Circuits and Signal Processing (AICSG), 2008 (submitted) J43. B. Yan, S. X-.D. Tan, L. Wu, “DeMOR: Decentralized model order reduction and simulation of linear networks with massive ports”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (submitted). J44. D. Li, S. X-.D. Tan, L. Wu, “ETBR: Extended truncated balanced realization method for on-chip power grid network Analysis”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (submitted).
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Symposia/Conference ProceedingsC1 X.-D. Tan, J.-R. Tong, P.-S. Tang, “Design tool integration and control using object oriented approach,” Proc. Int. Application Specific Integrated Circuits Conference (ASICON'94), Beijing P.R. China, Oct. 1994, pp.21-24. C2 X.-D. Tan, J.-R. Tong., P.-S. Tang, “Improved min-cut algorithm for multi-way VLSI network partitioning,” Proc. Int. Computer Aided Design and Graphics (CAD/Graphic'95), Wuhan P.R. China, Oct. 1995, pp. 651-656. C3 X.-D. Tan, J.-R. Tong, and P.-S. Tang, “An efficient multi-way algorithm for balance partitioning of VLSI circuits,” Proc. IEEE Int. Conf. on Computer Design (ICCD), Austin, TX, Oct. 1997, pp. 608-613. C4 C.-J. Shi, Y. Ye, and X.-D Tan, “Behavioral model optimization via sensitivity-enhanced genetic search,” Proc. IEEE/VIUF Int. Workshops on Behavioral Modeling and Simulation (BMAS'97), Washington DC, Oct. 1997, pp. 17-24. C5 C.-J. Shi and X.-D. Tan, “Symbolic analysis of large analog circuits by determinant decision diagrams,” Proc. IEEE International Conference on Computer-Aided Design (ICCAD'97), San Jose, CA . Nov. 1997, pp. 366-373. C6 C.-J. Shi and X.-D. Tan, “Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits,” Proc. IEEE Custom Integrated Circuits Conference (CICC98), Santa Clara, CA, May, 1998, pp. 463-466. C7 X.-D. Tan and C.-J Shi, “Hierarchical symbolic analysis of large analog circuits with determinant decision diagrams,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. VI, Monterey, CA. May 31-June 3, 1998, pp. 318-321. C8 X.-D. Tan and C.-J. Shi, “Balanced multi-level multi-way partitioning of large analog circuits for hierarchical symbolic analysis,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, China. Jan. 18-21, 1999, pp.1-4. C9 X.-D. Tan and C.-J. Shi, “Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams,” Proc. Design, Automation and Test in Europe (DATE'99), Munich, Germany. Mar. 10-13, 1999, pp. 448-453 C10 X.-D. Tan, C.-J. Shi, D. Lungeanu, J.-C. Lee, and L.-P. Yuan, “ Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings,” Proc. IEEE/ACM 36th Design Automation Conference (DAC), New Orleans, LA. June 1999, pp. 78-83. Best Paper Award (< 1%) C11 X.-D. Tan and C.-J. Shi. 2000, “Symbolic circuit-noise modeling and analysis via determinant decision diagrams,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'00), Yokohama, Japan. Jan. 2000, pp. 283-287. C12 X.-D. Tan and C.-J. Shi, “Fast power-ground network optimization using equivalent circuit modeling,” Proc. 38th IEEE/ACM Design Automation Conference (DAC’2001), Las Vegas, NE. June 2001, pp.550-554. C13 X.-D. S. Tan, C.-J. Richard Shi, “Parametric analog behavioral modeling based on cancellation-free DDDs”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), Santa Rosa, CA, Oct., 2002. C14 S. X.-D. Tan, C.-J. Shi, “Efficient DDD-based term generation algorithm for analog circuit behavioral modeling,” Proc. Asia South Pacific Design Automation Conference (ASP-DAC’03), Kitakyushu, Japan, Jan. 2003, pp.789-794. C15 Qi-De Qian and S. X.-D. Tan, “Advanced physical models for mask data verification and impacts on physical layout synthesis.” Proc. International symposium on quality electronic design (ISQED03), San Jose, March 2003, pp.125-130. C16 S. X.-D. Tan and J. Yang, “Hurwitz stable model reduction for non-tree structured RLCK circuits,” in Proc. 16th IEEE International System-on-Chip Conference (SOC), Portland OR, Sept. 2003. pp.239-242. C17 W. Guo and S. X.-D. Tan, “Circuit level alternating-direction-implicit approach to transient analysis of power distribution networks”, in Proc. 5th International Conference on ASIC (ASICON), Beijing China, Oct. 2003. pp.246-249, (Invited) C18 S. X.-D. Tan, “A general s-domain hierarchical network reduction algorithm”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, pp. 650-657, Nov. 2003. C19 J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan and Z. Pan “A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’04), pp.505-510, Yokohama, Japan, Jan. 2004. C20 S. X.-D. Tan and Z. Qi and H. Li, “Hierarchical modeling and simulation of large analog circuits”, Proc. Design, Automation and Test in Europe (DATE'04), Paris, France. pp. 740-741, Feb. 16-20, 2004. C21 Z. Pan, Y. Cai, S. X.-D. Tan, Z. Luo, X. Hong ,“Transient analysis of on-chip power distribution networks using equivalent circuit modeling”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’04), pp. 63-68, San Jose, CA , March 2004. C22 J. Yang and S. X.-D. Tan, “Behavioral modeling of analog circuits by dynamic semi-symbolic analysis”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, pp. V105-108, May, 2004. C23 J. Yang and S. X.-D. Tan, “An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, pp. V129-132, May, 2004. C24 W. Guo, S. X.-D. Tan, Z. Luo, X. Hong, “Partial random walk for large linear network analysis”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, pp. V173-176, May, 2004. C25 S. X.-D. Tan and W. Guo and Z. Qi, “Hierarchical approach to exact symbolic analysis of large analog circuits”, Proc. 41th IEEE/ACM Design Automation Conference (DAC’2004), pp.860-863, San Diego , CA, 2004. C26 R. Lysecky, F. Vahid, S. X.-D. Tan, “Dynamic FPGA routing for just-in-time FPGA compilation”, Proc. 41th IEEE/ACM Design Automation Conference (DAC’2004), San Diego , pp. 954-959, CA, 2004. C27 H. Yu, L. He and S. X.-D. Tan, “Compact macro-modeling for on-chip RF passive components”, Proc. IEEE International Conference on Communications, Circuits and Systems, Chengdu, vol. 2, pp. 199-202, China, 2004 . C28 J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan and Z. Pan, “Simultaneous wire sizing and decoupling capacitance budgeting for robust on-chip power delivery”, Intl. Workshop Power and Timing Modeling, Optimization and Simulation, (PATMOS’04), pp. 433-441, Greek. C29 L. Zhang, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, J. Fu, “Optimal wire sizing in the early stage design of on-chip power/ground (P/G) networks”, Int, Conf. Solid State and Integrated Circuit Technology (ICSICT’04), Beijing, China, Oct. 2004. C30 X. Wang, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, “EQUADI: A linear complexity algorithm for transient analysis for power/ground(P/G) networks in ASICs”, Int, Conf. Solid State and Integrated Circuit Technology (ICSICT’04), Beijing, China, Oct. 2004. C31 Y. Zou, Y. Cai ,Q. Zhou, X. Hong, S. X.-D. Tan, “A fast delay analysis algorithm for the hybrid structured clock network”, in Proc. Int. Conf. Computer Design (ICCD), pp., 2004 C32 Z. Qi , S. X-.D. Tan, H. Yu , L. He and P. Liu, “Wideband modeling of RF/analog circuits via hierarchical multi-point model order reduction”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’05), pp.224-229. Shanghai, China, Jan. 2005. C33 H. Yu, Z. Qi, L. He and S. X.-D. Tan, “A wideband realizable circuit-reduction for RLCM interconnects”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’05), pp.111-114, Shanghai, China, Jan. 2005. C34 J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan and Z. Pan, “VLSI on-chip power/ground network optimization considering decap leakage currents”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’05), pp.735-738, Shanghai, China, Jan. 2005. C35 Z. Pan, Y. Cai, Z. Luo, X. Hong, S. X.-D. Tan, W. Hou, L. Wu, “Relaxed hierarchical power/ground grid analysis”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’05), pp.1090-1093, Shanghai, China, Jan. 2005. C36 Y. Zou, Q. Zhou, Y. Cai, X. Hong and S. X-.D. Tan, “Analysis of buffered hybrid structured clock networks”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’05), pp.93-98, Shanghai, China, Jan. 2005. C37 P. Liu, Z. Qi and S. X.-D. Tan, “Passive hierarchical model order reduction and realization of RLCM circuits”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’05), pp. 603-608, San Jose, CA , March 2005. C20 Z. Qi, and H. Li, S. X.-D. Tan, L. Wu, Y. Cai, X. Hong ,“Fast decap allocation algorithm for robust on-chip power delivery”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’05), pp. 542-547, San Jose, CA , March 2005. C21 R. Lysecky, F. Vahid, S. X.-D. Tan, “A study of the scalability of on-chip routing for just-in-time FPGA compilation”, Proc. IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM’05), Napa, CA, April 2005. C22 H. Li, Z. Qi, S. X-D. Tan, L. Wu, Y. Cai, X. Hong, “Partitioning-based approach to fast on-chip decap budgeting and minimization”, Proc. IEEE/ACM Design Automation Conference (DAC’2005), pp. 170-175, CA, 2005. Best Paper Award Nomination (16 out of 735 submission, 2%) C23 J. Shi, Y. Cai, X. Hong, S. X-D. Tan, “Efficient simulation of power/ground networks with packages and vias”, Intl. Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS’05), pp.257-266, Leuven, Belgium, Sep. 2005. C24 P. Liu, Z. Qi, A. Aviles, S. X.-D. Tan, “A general method for multi-port active network reduction and realization”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.7-12, San Jose, CA, Sept., 2005. C25 Z. Qi, S. X.-D. Tan, P. Liu, “Efficient analog circuit modeling by Boolean logic operations”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp. 76-81, San Jose, CA, Sept., 2005. C26 J. Yang, S. X.-D. Tan, Z. Qi, M. Gawecki, “Hierarchical symbolic piecewise-linear circuit analysis”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.140-145, San Jose, CA, Sept., 2005. C27 H. Yu, L. He, S. X.-D. Tan, “Block structure preserving model reduction for linear circuits with large numbers of ports”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.1-6, San Jose, CA, Sept., 2005. C28 H. Li, P. Liu, Z. Qi, L. Jin, W. Wu, S. X.-D. Tan, and J. Yang, “Efficient thermal simulation for run-time temperature tracking and management”, in Proc. Int. Conf. Computer Design (ICCD), pp.130-133, San Jose, CA 2005. C29 Z. Qi, J. Fan, H. Li, S. X.-D. Tan, Y. Cai, X. Hong, “On-chip decoupling capacitor budgeting by sequence of linear programming”, in Proc. 6th International Conference on ASIC (ASICON), pp.70-73, Beijing China, Oct. 2005. (Invited). C30 P. Liu, S. X.-D. Tan, H. Li, Z. Qi, J. Kong, B. McGaughy, L. He, “An efficient method for terminal reduction of interconnect circuits considering delay variations”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), pp. 821-826, San Jose, CA, Nov. 2005. C31 P. Liu, Z. Qi, H. Li, L. Jin, W. Wu, S. X.-D. Tan and J. Yang, “Fast thermal simulation for architecture level dynamic thermal management”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), pp.639-644, San Jose, CA, Nov. 2005. C32 J. Shi, Y. Cai, S. X.-D. Tan, X. Hong, “ Efficient early stage resonance estimation techniques for C4 package”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’06), pp.826-831, Yokohama City, Japan, Jan. 2006. C33 J. Fan, I. Liao, S. X.-D. Tan, Y. Cai, X. Hong, “Localized on-chip power delivery network optimization via sequence of linear programming”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’06), pp.272-277, San Jose, CA , March 2006. C34 P. Liu, S. X.-D. Tan, B. McGaughy, L. Wu, “Compact reduced order modeling for multiple-port interconnects”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’06), pp.413-418, San Jose, CA, March 2006. C35 A. Kahng, B. Liu, S. X-D. Tan, ”SMM: Scalable analysis of power delivery networks by stochastic moment matching”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’06), pp.638-643, San Jose, CA , March 2006. C36 J. Shi, Y. Cai, X. Hong, S. X.-D. Tan, “High accurate pattern based precondition method for extremely large power/ground grid analysis”, ACM Symposium on Physical Design (ISPD’06), pp.108-113, San Jose, CA, April 2006. C37 A. Kahng, B. Liu, S. X.-D. Tan, “Efficient decoupling capacitor planning via convex programming methods”, ACM Symposium on Physical Design (ISPD’06), pp.102-107, San Jose, CA, April 2006. C38 W. Wu, L. Jin, J. Yang, P. Liu and S. X.-D. Tan “Efficient method for functional unit power estimation in modern microprocessors”, Proc. IEEE/ACM Design Automation Conference (DAC’06), pp.554-557, CA, 2006. C39 N. Mi, J. Fan, S. X.-D. Tan, “Statistical analysis of power grid networks considering lognormal leakage current variations with spatial correlation”, in Proc. Int. Conf. Computer Design (ICCD), pp.56-62, San Jose, CA 2006. C40 P. Liu, S. X.-D. Tan, B. Yan, B. McGaughy “An extended SVD-based terminal and model order reduction algorithm”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.44-49, San Jose, CA, Sept., 2006. C41 J. Fan, N. Mi, S. X.-D. Tan, “Variational compact modeling and simulation for linear dynamic systems”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.17-22, San Jose, CA, Sept., 2006. C42 N. Mi, J. Fan, S. X.-D. Tan, “Simulation of power grid networks considering wires and lognormal leakage current variations”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.73-78, San Jose, CA, Sept., 2006. C43 B. Yan, S. X-.D. Tan, P. Liu, B. McGaughy, “Passive interconnect macromodeling via balanced truncation of linear systems in descriptor form”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’07), pp. 355-360, Yokohama City, Japan, Jan. 2007. C44 Y. Zou, Y. Cai, X. Hong, S. X.-D. Tan, “Practical implementation of stochastic parameterized model order reduction via Hermite polynomial chaos”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’07), pp.367-372, Yokohama City, Japan, Jan. 2007. C45 L. Kang, Y. Cai, X. Hong, S. X.-D. Tan, “Fast decoupling capacitor budgeting for power/ground networks using random walk approach”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’07), pp.751-756, Yokohama City, Japan, Jan. 2007. C46 B. Yan, P. Liu, S. X.-D. Tan, B. McGaughy, “Passive modeling of interconnects by waveform shaping”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’07), pp.356-361, San Jose, CA, March 2007. C47 N. Mi, B. Yan, S. X.-D. Tan, J. Fan, H. Yu “General block structure-preserving reduced order modeling of linear dynamic circuits”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’07), pp. 633-638, San Jose, CA , March 2007. C48 J. Fan, N. Mi, S. X.-D. Tan, Y. Cai and X. Hong, “Statistical model order reduction for interconnect circuits considering spatial correlations”, Proc. Design, Automation and Test in Europe (DATE'07), pp. 1508-1513, Nice, France , April 2007. C49 B. Yan, S. X-.D. Tan, P. Liu, B. McGaughy, “SBPOR: second-order balanced truncation for passive model order reduction of RLC circuits”, Proc. IEEE/ACM Design Automation Conference (DAC’07), pp.158-161, San Diego, CA, 2007. C50 N. Mi, S. X.-D. Tan, P. Liu, J. Cui, Y. Cai and X. Hong, “Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), pp.48-53, San Jose, CA, Nov. 2007. C51 D. Li, S. X-.D. Tan, and M. Tirumala, “Behavioral thermal modeling for quad-core microprocessors”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp. 22-27, San Jose, CA, Sept., 2007. C52 J. Fan, G. Yu, J. Tan and S. X.-D. Tan, “Modeling and analysis of biological cells in DRAM implementation”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.90-93, San Jose, CA, Sept., 2007. C53 J. Fan, N. Mi, S. X.-D. Tan, “Voltage drop reduction for on-chip power delivery considering leakage current variations”, in Proc. Int. Conf. Computer Design (ICCD), Lake Tahoe, pp. 78-83, CA 2007. C54 W. Wu, J. Yang, S. X.-D. Tan, S.-L. Lu, “Improving the reliability of on-chip caches under process variations”, in Proc. Int. Conf. Computer Design (ICCD), Lake Tahoe, pp. 325-332, CA 2007. Best Paper Award (<2%). C55 X. Yuan, J. Fan, B. Liu, S. X.-D. Tan, “Stochastic based extended Krylov subspace method for power/ground network analysis”, in Proc. 6th International Conference on ASIC (ASICON’07), Guilin, China, Oct. 2007. (Invited). C56 L. Kang, Y. Cai, J. Shi, X. Hong, S. X.-D. Tan, and X. Wang, “Simultaneous switching noise consideration for power/ground network optimization”, In Proc. Computer Aided Design &Computer Graphic (CAD&CD’07), Beijing, Oct 2007. C57 D. Li, S. X.-.D. Tan, and M. Tirumala, “Architecture-level thermal behavioral characterization for multi-core microprocessors”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’08), pp.456-461, Seoul, Korea, Jan. 2008. C58 D. Li, S. X.-D. Tan, “Hierarchical Krylov subspace reduced order modeling of large RLC circuits”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’08), pp.170-175, Seoul, Korea, Jan. 2008. C59 D. Li, S.X.-D. Tan, B. McGaughy, “ETBR: Extended truncated balanced realization method for on-chip power grid network analysis”, Proc. Design, Automation and Test in Europe (DATE'08), pp.432-437, Munich, Germany, March 2008. C60 Z. Luo, S. X.-D. Tan, “Statistic analysis of power/ground networks using single-node SOR method”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’08), pp. 867-872, San Jose, CA , March 2008. C61 P. Liu, S. X.-D. Tan, W. Wu and M. Tirumala, “FEKIS: A fast architecture-level thermal analyzer for online thermal regulation”, Proc. IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI’08), pp. 441-416, Orlando, 2008. C62 J. Cui, G. Chen, R. Shen, S. X.-D. Tan, W. Yu, J. Tong, “Variational capacitance modeling using orthogonal polynomial method”, Proc. IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI’08), pp. 23-28, Orlando, 2008. C63 B. Yan, L. Zhou, S. X.-D. Tan, J. Chen, B. McGaughy, “DeMOR: Decentralized model order reduction of interconnects with massive ports”, Proc. IEEE/ACM Design Automation Conference (DAC’08), pp. 409-414, Anaheim, CA, 2008. C64 B. Yan, H. Wang, S. X.-D. Tan, “A survey of RLCK reduction and simulation methods by fast truncated balanced realization”, Int, Conf. Solid State and Integrated Circuit Technology (ICSICT’08), Beijing, China, Oct. 2008. (invited) C65 B. Yan, S. X.-D. Tan, G. Chen, L. Wu, “Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2008. C66 D. Li, S. X.-.D. Tan, E. H. Pacheco, M. Tirumala, “Parameterized transient thermal behavioral modeling for chip multiprocessors”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2008.
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