Statistical
Characterization and Simulation of VLSI Circuits Considering Process Variations
Dr. Sheldon Tan (PI), UCR
Collaborators:
Dr. Yici
Cai, Tsinghua University, China
Dr. Hao Yu, NTU, Singapore
Dr.
Jinjun Xiong, IBM T. J. Watson Research Center, USA
Dr.
Chandu Visweswariah, IBM, USA
David Hosson Shin, Yan Zhu
Ruijing Shen, Duo Li, Zhigang Hao, Ning Mi
National Science Foundation, ÒSHF: Small: Variational and Bound
Performance Analysis of Nanometer Mixed-Signal/Analog CircuitsÓ, (CCF-1116882),
9/1/2011-8/30/2014, PI: Sheldon Tan
National Science Foundation, ÒIRES:
Development of Global Scientists and Engineers by Collaborative Research on
Variation-Aware Nanometer IC DesignÓ, (OISE-1130402), 9/1/2011-8/30/2014, PI:
Sheldon Tan, co-PI: Yici Cai
National Science Foundation, ÒUS-Singapore
Planning Visit: Collaborative Research on Design and Verification of 60Ghz
RF/MM Integrated CircuitsÓ, (OISE-1051797), 4/1/2011-3/30/2013, PI:
Sheldon Tan, co-PI: Hao Yu.
2011 UC MEXUS-CONACYT Collaborative Research Grants, ÒSymbolic
and Statistical Modeling and
Analysis Techniques for Analog/Mixed-Signal Nanometer Integrated CircuitsÓ,
2011-2013 academic year , 9/1/2011-2/31/2013, PI:
Sheldon Tan
2009 UC MEXUS-CONACYT Collaborative Research
Grant,
ÒSymbolic modeling and reduction for
analog/RF circuits and on-chip interconnectÓ, Aug
2009 to Jan 2011, PI, co-PI: Dr. Esteban Tlelo-Cuautle.
National Science Foundation, ÒIRES:
Development of Global Scientists by Research Collaborations on Simulation and
Optimization of Nanometer Integrated SystemsÓ, (OISE-0623038), 9/1/2006-8/30/2009, PI:
Sheldon Tan, co-PI: Yici Cai
National Science Foundation, ÒCAREER: Career Development
Plan: Behavioral Modeling, Simulation and Optimization for Mixed-Signal System
in a ChipÓ, (CCF-0448534, a number of REU supplements),
6/1/2005-5/31/2011. PI: Sheldon Tan.
This
proposal tries to addresses the fundamental and emerging challenges in
performance analysis under process parameter variability for
analog/mixed-signal and VLSI
circuits. The main goal of this program is to develop novel and efficient
non-Monte-Carlo techniques for worst-case and statistical analysis of
analog/mixed-signal circuits.
Specficially,
we seek the following goals for the
project
(1) Development of novel worst-case analysis methods
for analog/mixed-signal circuits based on graph-based symbolic analysis,
affine-like interval arithmetic and KharitonovÕs functions. The new method will
first build variational transfer functions from linearized analog circuit by
determinant decision diagram (DDD) based symbolic analysis and affine-like
interval arithmetic. Then the performance bounds will be computed by
KharitonovÕs functions from the variational transfer functions. We will
investigate more conservative affine-like interval arithmetic to reduce
conservation. We will investigate the performance bounds in the time domains
given frequency domain bounds;
(2) Development of fast non-Monte-Carlo statistical
analysis methods to calculate mismatch due to process variations. We model the
problem as solving nonlinear stochastic differential-algebra-equations.
Nonlinear stochastic methods (Galerkin or collocation methods) and
trajectory-piecewise-linear macromodeling method with incremental subspace
aggregation will be applied to solve the resulting problems.
(3) Fast
Monto-Carlo or other statisitical methods for rate event (high sigma) and more
variables (high dimentional) statistiical analysis.
á IBM Watson
Research Center, Yorktown Height, NY, ÒVariational Analysis for Large Power
Delivery Networks and Full-Chip Leakage Powers of Nanometer VLSI SystemsÓ, Nov.
5, 2008.
á Shanghai
Jiao Tong University, School of Microelectronics, Shanghai, China, ÒVariational
Analysis of Full-Chip Leakage Power in Nanometer VLSI SystemsÓ, June 16,
2009.
á Xi'an
Institute of Post & Telecommunications, Dept of Computer Science, Xi'an,
Shaanxi Province, China, ÒVariational Analysis of Clock Networks
Considering Environmental UncertaintyÓ, July 8, 2009.
á XiÕan Jiao
Tong University, Dept of Electrical Engineering, XiÕan, Shaanxi Province, China,
ÒVariational Analysis of Clock Networks Considering Environmental UncertaintyÓ,
July 10, 2009.
á Fudan Univ.
Shanghai, China, ÒStatistical Analysis of Full-Chip Leakage Power in Nanometer
VLSI SystemsÓ, July. 23, 2010.
á Shanghai Jiao Tong University, School of Microelectronics, Shanghai, China,
ÒPerformance bound analysis of analog circuits considering process variationÓ,
May 30, 2011.
á The University of Hong Kong, Department of Electrical and
Electronic Engineering, Hong Kong, China,
ÒGraph-based Parallel and Statistical Analysis of Analog Circuits Based on GPU
PlatformsÓ, Hong Kong, Aug. 23, 2011.
á The EDA workshop, Department of Electrical Engineering,
National Taiwan University, Taiwan, ÒPerformance Bound Analysis for Analog
Circuits Under Process VariationsÓ, Sept 10, 2011.
á
International Workshop
on Emerging Circuits and Systems (IWECSÕ12), Shanghai
Jiao Tong University, Shanghai, China, ÒParallel Computing and Simulation for VLSI
systemsÓ, Aug. 9, 2012.
á INAOE (Institute
National Astrophysics, Optical and Electrics), Department
of Electrical Engineering, Puebla, Mexico , ÒFast GPU-accelerated
Sparse Matrix-Vector MultiplicationÓ, May 3, 2013.
As VLSI technology scales into
the nanometer regime, chip design engineering face several challenges in
maintaining historical rates of performance improvement and capacity increase
with CMOS technologies. One profound change in the chip design business is that
engineers can't put the design precisely into the silicon chips. Chip
performance, manufacture yield and lifetime become unpredictable at the design
stage. Chip performance, manufacture yield and lifetime can't be determined
accurately at the design stage. The main culprit is that many chip parameters
-- such as oxide thickness due to chemical and mechanical polish (CMP) and
impurity density from doping fluctuations -- can't be determined precisely, and
thus are unpredictable. The so-called manufacture process variations start to
play a big role and their influence on the chip's performance, yield and
reliability becomes significant.
As a result, how to efficiently
and accurately assess the impacts of the process variations of interconnects in
the various physical design steps are critical for fast design closure, yield improvement,
cost reduction of VLSI design and fabrication processes. The design
methodologies and design tools from system level down to the physical levels
have to embrace variability impacts on the VLSI chips, which calls for
statistical/stochastic based approaches for designing 90nm and beyond VLSI
systems.
In this regard, it is
imperative to develop new design methodologies to consider the impacts of
various process and environmental uncertainties and elevated temperature on chip
performance. Variational impacts and thermal constraints have to be
incorporated into every steps of design process to ensure the reliable chips
and profitable manufacture yields. The design methodologies and design tools
from system level down to the physical levels have to consider variability and
thermal impacts on the chip performance, which calls for new statistical and thermal-aware
optimization approaches for designing nanometer VLSI systems.
The PIÕs group at UCR has been
working on statistical modeling and simulation of VLSI systems since 2006 and
has made a number of contributions in this field. We have proposed statistical
on-chip power grid analysis approaches based spectral stochastic method[ J1,J2,J5,C1,C3,C5,C7,C10],
stochastic model order reduction methods [C2C4],
stochastic capacitance and inductance extraction techniques [J3,C8,
C15],
statistical leakage and power (total and dynamic power) analysis techniques [J4,C11,C13,C14,C16,C17],
performance bound and mismatch analysis of analog and mixed-signal circuits [C9,
C12,C18],
statistical timing analysis [J6,C9]
and variational impact analysis on the on-chip cache design [C6].
A book summarized our works in a systemic way will be published by Springer in
2012 [B1].
Book and book chapter publications
B1. Ruijing Shen, Sheldon X.-D. Tan and Hao Yu, Statistical
Performance Analysis and Modeling Techniques for Nanometer VLSI Designs, Springer Publisher, March 2012, ISBN-10: 1461407877.
B2.
Sheldon X.-D. Tan, Ruijing Shen,
ÒChip-Level Statistical Leakage Modeling and AnalysisÓ, Chapter in Recent Advancements in Modeling of
Semiconductor Processes, Circuits and Chip-Level Interactions, Rasit Onur
Topaloglu, and Peng Li (Editors), Bentham Publishing (www.ebook-engineering.org), 2010 (in press).
B3.
Xue-Xin Liu, Hao Yu, Hai Wang, Sheldon
X.-D. Tan, ÒAnalog mismatch analysis by stochastic nonlinear macromodelingÓ,
Chapter in
ÒAnalog Circuits: Applications, Design and PerformancesÓ, E. Tlelo-Cuautle (Editor), NOVA Science
Publishers Inc. ISBN: 978-1-61324-355-8.
B4. Guoyong
Shi, Sheldon X.-D. Tan, Esteban
Tlelo-Cuautle, ÒAdvanced
Symbolic Analysis for VLSI Systems -- Methods and ApplicationsÓ, Springer Publisher, 2014, ISBN
978-1-4939-1103-5
J1.
N. Mi, J. Fan, S. X.-D. Tan, Y. Cai
and X. Hong, ÒStatistical
analysis of on-chip power delivery networks considering lognormal leakage
current variations with spatial correlationsÓ, IEEE Transaction on Circuit
and System I (TCAS-I), vol. 55,
no. 7, pp.2064-2075, August, 2008.
J2.
N. Mi, S. X.-D. Tan, Y. Cai and X. Hong, ÒFast
variational analysis of on-chip power grids by stochastic extended Krylov
subspace methodÓ, IEEE Transaction on Computer-Aided Design of
Integrated Circuits and Systems (TCAD), vol. 27, no. 11, pp. 1996-2006,
2008.
J3.
R. Shen, S. X.-D. Tan, J. Cui, W. Yu, Y. Cai and G. Chen, ÒVariational
capacitance extraction and modeling
based on orthogonal polynomial methodÓ, IEEE Transactions
on Very Large Scale Integrated Systems
(TVLSI), vol.18, no.11,
pp1556-1565, 2010.
J4.
R. Shen, S. X.-D. Tan, N. Mi and Y. Cai, ÒStatistical
modeling and analysis of chip-level leakage power by spectral stochastic methodÓ, Integration, The VLSI Journal, vol. 43, no. 1, pp.
156-165, January 2010. (online
permanent DOI Link)
J5.
D. Li, S. X.-D.
Tan, ÒStatistical
analysis of large on-chip power grid networks by variational reduction schemeÓ, Integration, The VLSI Journal,
vol.
43, no. 2, pp.167-175, April, 2010.
J6.
H. Wang, H. Yu, S. X.-D. Tan, ÒFast
timing analysis of clock networks considering environmental uncertaintyÓ, Integration, The VLSI Journal, online available at http://dx.doi.org/10.1016/j.vlsi.2011.03.001
J7.
Z. Hao, S. X.-D. Tan, E. Tlelo-Cuautle, J. Relles, C. Hu, W. Yu, Y. Cai
and G. Shi, ÒStatistical
extraction and modeling of inductance considering spatial correlationÓ,
Analog Integr Circ Sig Process, July 2011. DOI:
10.1007/s10470-011-9720-8.
J8.
F. Gong, X. Liu, H. Yu, S. X.-D. Tan, J. Ren and L. He, "A fast
non-Monte-Carlo yield analysis and optimization by stochastic orthogonal polynomials",
ACM Transactions on Design Automation of
Electronic Systems (TODAES), vol. 17, no.1, pp10:1-10:23, January 2012. 10.1145/2071356.2071366
J9.
Z. Hao, S. X.-D. Tan, G. Shi, ÒStatistical
full-chip total power estimation considering spatially correlated process
variationsÓ, Integration, The VLSI Journal, Vol. 73, no. 1, 2012. doi:10.1016/j.vlsi.2011.12.004
J10. R. Shen, S. X.-D. Tan, H. Wang, J. Xiong, ÒFast statistical full-chip leakage analysis
for nanometer VLSI systemsÓ,
ACM Transactions on Design Automation of
Electronic Systems (TODAES), vol. 17, no. 4, pp.51:1--51:19, Sept. 2012. 10.1145/2348839.2348855
J11. Z.
Hao, G. Shi, S. X.-D. Tan, E. Tlelo-Cuautle, ÒSymbolic moment computation for
statistical analysis of large interconnect networksÓ, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 21, no. 5, pp. 944-957, May
2013
J12.
X. Liu, S.
X.-D. Tan, A.
Palma-Rodriguez, E. Tlelo-Cuautle, G. Shi, and Y. Cai, ÒPerformance bound analysis of analog circuits
in frequency and time domain considering process variationsÓ, ACM
Transactions on Design Automation of Electronic Systems (TODAES), vol. 19, no. 6, Dec. 2013.
C1 N. Mi, J. Fan, S. X.-D. Tan, ÒStatistical analysis of power grid networks
considering lognormal leakage current variations with spatial correlationÓ, in Proc. Int. Conf. Computer Design (ICCD),
pp.56-62, San Jose, CA 2006.
C2
J. Fan, N. Mi, S. X.-D. Tan, ÒVariational compact modeling and
simulation for linear dynamic systemsÓ, IEEE International Workshop on Behavioral
Modeling and Simulation (BMAS),
pp.17-22, San Jose, CA, Sept., 2006.
C3
N. Mi, J. Fan, S. X.-D. Tan, ÒSimulation of power grid networks considering
wires and lognormal leakage current variationsÓ, IEEE International Workshop on
Behavioral Modeling and Simulation (BMAS),
pp.73-78, San Jose, CA, Sept., 2006.
C4
J. Fan, N. Mi, S. X.-D. Tan, Y. Cai and X. Hong, ÒStatistical model order reduction for
interconnect circuits considering spatial correlationsÓ, Proc. Design, Automation and Test in Europe (DATE'07), pp. 1508-1513, Nice, France, April 2007.
C5 N.
Mi, S. X.-D. Tan, P. Liu, J. Cui, Y. Cai and X. Hong, ÒStochastic extended Krylov subspace
method for variational analysis of on-chip power grid networksÓ, Proc. IEEE/ACM
International Conf. on Computer-Aided Design (ICCAD), pp.48-53, San Jose, CA, Nov. 2007.
C6
W. Wu, J.
Yang, S. X.-D. Tan, S.-L. Lu, ÒImproving the reliability of on-chip
caches under process variationsÓ, in Proc. Int. Conf. Computer Design (ICCD), Lake
Tahoe, pp. 325-332, CA 2007. Best Paper Award (<2%).
C7 X.
Yuan, J. Fan, B. Liu, S. X.-D. Tan, ÒStochastic based extended Krylov subspace
method for power/ground network analysisÓ, in Proc.
7th International Conference on ASIC (ASICONÕ07), Guilin, China, Oct. 2007.
(Invited).
C8 J.
Cui, G. Chen, R. Shen, S. X.-D. Tan,
W. Yu, J. Tong, ÒVariational capacitance modeling
using orthogonal polynomial methodÓ, Proc. IEEE/ACM International Great Lakes
Symposium on VLSI (GLSVLSIÕ08), pp. 23-28,
Orlando, 2008.
C9 H. Wang, H. Yu, S. X.-D. Tan, ÒFast analysis of non-tree clock network
considering environmental uncertainty by parameterized and incremental
macromodelingÓ, Proc.
Asia South Pacific Design Automation Conference (ASP-DACÕ09), pp. 379-384,
Yokohama, Japan, Jan. 2009.
C10 D. Li, S. X.-.D. Tan, G. Chen and X. Zeng, ÒStatistical analysis of on-chip power
grid networks by variational extended truncated balanced realization methodÓ Proc. Asia South Pacific Design Automation
Conference (ASP-DACÕ09), pp. 272-277, Yokohama, Japan, Jan. 2009.
C11 R.
Shen, N. Mi, S. X.-D. Tan, Y. Cai, X. Hong, ÒStatistical
modeling and
analysis of chip-level leakage power by spectral stochastic methodÓ, Proc. Asia South Pacific Design Automation Conference
(ASP-DACÕ09), pp. 161-166, Yokohama, Japan, Jan. 2009.
C12 H.
Yu, X. Liu, H. Wang, S. X.-D. Tan, ÒA fast analog mismatch analysis by an
incremental and stochastic trajectory piecewise linear macromodelÓ, Proc. Asia South Pacific Design Automation Conference
(ASP-DACÕ10), pp.211-216, Taipei, Taiwan, Jan. 2010.
C13 R.
Shen, S. X.-D. Tan,
J. Xiong, ÒA linear statistical analysis for
full-chip leakage power with spatial correlationÓ, Proc. IEEE/ACM International
Great Lakes Symposium on VLSI (GLSVLSIÕ10), pp.27-232, Providence, RI, May,
2010.
C14 R.
Shen, S. X.-D. Tan,
J. Xiong, ÒA
linear algorithm for full-chip statistical leakage power analysis considering
weak spatial correlationÓ, Proc. IEEE/ACM Design
Automation Conference (DACÕ10),
pp.481-486, Anaheim, CA, 2010.
C15 J.
Relles, M. Ngan, E. Tlelo-Cuautle, S. X.-D. Tan, C. Hu, W. Yu and Y. Cai, ÒStatistical extraction and modeling
of 3D inductance with spatial correlationÓ, IEEE International Workshop on Symbolic and Numerical Methods, Modeling
and Applications to Circuit Design (SM2ACD), Tunisia,
October 5-6, 2010.
C16 Z.
Hao, R. Shen, S. X.-D. Tan, B. Liu, G. Shi and Y. Cai, ÒStatistical full-chip dynamic power
estimation considering spatial correlationsÓ, Proc. Int. Symposium. on Quality Electronic
Design (ISQEDÕ11), San Jose, CA, pp677-782, March 2011.
C17 Z.
Hao, S. X.-D. Tan, G. Shi, ÒAn efficient statistical chip-level total
power estimation method considering process variations with spatial correlationÓ, Proc. Int. Symposium. on Quality Electronic
Design (ISQEDÕ11), pp.671-676, San Jose, CA, March 2011.
C18
Z. Hao, S. X.-D. Tan, R. Shen, G. Shi, ÒPerformance bound analysis of analog
circuits considering process variationsÓ, Proc. IEEE/ACM Design Automation
Conference (DACÕ11) ,
pp.310-315, San Diego, CA, June 2011.
C19 X. Liu, S. X.-D. Tan, Z.
Hao, G. Shi, ÒTime-domain performance bound analysis of analog circuits considering
process variationsÓ, Ó, Proc.
Asia South Pacific Design Automation Conference (ASP-DACÕ12), Sydney, Australia,
pp.535-540, Jan. 2012.
C20 X.
Liu, S. X.-D. Tan, and H. Wang, ÒParallel
statistical analysis of analog circuits by GPU-accelerated graph-based approachÓ, Proc. Design, Automation and Test in Europe (DATE'12), pp.852-857, Dresden,
Germany, March
2012.
C21 R. Shen, S.
X.-D. Tan and X. Liu, ÒA new
voltage binning technique for yield improvement based on graph theoryÓ, Proc. Int. Symposium on Quality Electronic
Design (ISQEDÕ12), San Jose, CA,
March 2012.
C22 S.
Rodriguez-Chavez , E. Tlelo-Cuautle, A. Palma-Rodriguez, S. X.-D. Tan, ÒSymbolic
DDD-based tool for the computation of noise in CMOS analog circuitsÓ, 8th International Caribbean Conf.
on Devices, Circuits and Systems (ICCDCS), Playa del Carmen, Mexico, March
2012.
C23 A.
Palma-Rodriguez, S. Rodriguez-Chavez , E. Tlelo-Cuautle, S. X.-D. Tan, ÒDDD-based
symbolic sensitivity analysis of active filtersÓ, 8th International Caribbean Conf. on Devices, Circuits and
Systems (ICCDCS), Playa del Carmen, Mexico, March 2012.
C24 X.
Liu, A.
Palma-Rodriguez
, S. Rodriguez-Chavez, S.
X.-D. Tan, E. Tlelo-Cuautle,
Y. Cai, ÒPerformance
bound and yield analysis for analog circuits under process
variationsÓ,
Proc. Asia South Pacific Design Automation Conference (ASP-DACÕ13), pp.761-766, Yokohama, Japan, Jan.
2013.
C25 T. Yu, S. X.-D. Tan, Y. Cai, and P. Tang, ÒTime-domain
performance bound analysis for analog and interconnect circuits considering
process variationsÓ, Proc. Asia South
Pacific Design Automation Conference (ASP-DACÕ14), Singapore, Singapore,
Jan. 2014.
C26 A. Zhang, G. Shi, S. X-.D. Tan, J. Cheng, ÒSimultaneous SNR and SNR-variation optimization
for Sigma-Delta modulator designÓ, Int, Conf. Solid State and Integrated
Circuit Technology (ICSICTÕ04),
Guilin, China, Oct. 2014.
C27 Y. Zhu, S. X.-D. Tan, ÒGPU-accelerated parallel
Monte Carlo analysis of analog circuits by hierarchical graph-based solverÓ, Proc. Asia South Pacific Design Automation
Conference (ASP-DACÕ15), Chiba, Japan, Jan. 2015.