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Pradyumna Goli
Graduate Student Nano Device Laboratory Department of Electrical Engineering University of California Riverside.
Ph: (951)-288-1177 Email: pgoli at ee dot ucr dot edu |



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It all started here |

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Know me |


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What am i? |
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Quick links |
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Know me |
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"Imagination is more important than Knowledge” Albert Einstein |
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About me |

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Current Status |
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Research Interests |
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Objectives |


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What am I ? |
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"Anyone who has never made a mistake has never tried anything new” Albert Einstein |
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Education |
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Research work |
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Certifications and Memberships |
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Work Experience |
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Career projects |
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Academic Projects |
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Personal Projects |
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Honors |


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"Education is what remains after one has forgotten everything he learned in school” Albert Einstein |
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Technical Proficiency |









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And the story goes on |


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Specialities |
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I am currently a graduate student, pursuing my Masters in Electrical Engineering with Nano materials, devices and circuits as my specialization. I am member of Nano device Laboratory headed by Dr Alexander A Balandin. I obtained my Bachelors Degree from Electronics and Computers Engineering from Jawaharlal Nehru Technological University, Hyderabad , India. I am a certified in VLSI backend design by Cadence and University of California, Santacruz– extension. I am an active volunteer of Art of living which is one of UN’s largest volunteer-based NGO |
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University of California, Riverside Masters of Science in Electrical Engineering with Nano materials, devices and circuits as my specialization Advisor: Dr Alexander A Balandin GPA: 3.7/4.0
University of California, Santacruz-extension Diploma in VLSI Layout Design
Sreenidhi Institute of Science and Technology, Andhra Pradesh, India Bachelor of technology in Electronics and Computers Engineering, June 2007 Dissertation: Implementation of RISC Processor using VHDL. |
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Research Associate, Nano Device Laboratory, University of California Riverside Advisor: Dr Alexander A Balandin Role: Performed data collection, analysis on graphene. |
Sep 2008 – Present |
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Volunteer : Took part in Mission Green Earth (Joint venture of The Art of Living and UNEP) for 10 billion plantation across the globe. |
May 2008 – Jul 2008 |
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Internship: TTM (I) Pvt Ltd, Hyderabad, India as layout design Engineer. |
Sep 2007 – Apr 2008 |
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Block Level Design (Block of Hierarchical Design) |
Full Chip Design (Flat) |
Full Chip Design (Flat) |
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Technology |
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180 nm (TSMC) |
180 nm (UMC) |
180 nm (TSMC) |
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Gate Count |
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107,000 |
122,400 |
61,369 |
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Macros |
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04 |
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- |
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Blocks/Cells/IOs |
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12/24,800/120 |
4/11,342 /71 |
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Frequency |
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50 MHz |
150 MHz |
71.43 MHz |
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Tools |
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Cadence-SOC Encounter, Mentor Graphics-Calibre. |
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Duration |
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3 months |
2.5 months |
1.5 months |
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Scope |
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It involved performing sanity checks, data preparation, Uniquify the net list, floor planning, power planning, placement, trial route, RC Extract, timing analysis, CTS, Detail Route, GDS-II out, DRC and LVS.. |
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