Tradeoff Analysis: JPEG Decoder

Team: Renato Jareno, Jectofer Dumpit, Jerome Pasion, Miguel Carrillo

Project

Total Cost

Unit Cost

Size

Team Size

Performance 

Flexibility

Time-To-Prototype

Time-To-Market

Power

Maintainability

Usability

XS40

JPEG Decoder

 

 


Xilinx XS40 Board (including FPGA, 8051, VGA interface) ~$200

(Available from professor)


Xilinx SDK ~$500

(On UCR machines)

8051 Compilers ~OpenSource  

(Keil Compiler can be used)

 

Parts:

Black box ~$3

Button ~$1

Wires/Solder ~$1

Protoboard ~$5


VGA Monitor ~$0 (use one from home)

Total: $10

Xilinx XS40 Board: 6" x 2" x 1" (approx.)

 

2 People: Feasible

3 People: Definitely feasible, but would require more features

4 People:  Definitely requires more functionality.  With 4, XP can be used to our advantage (2 people on uC part, 2 on FPGA)  

100MHz programmable oscillator (50MHz by default) for FPGA

9,000 gates

 

32K SRAM (128K on the XL)

 

8051 uC

 

 

RS-232 port / UARTs for future peripheral add ons and serial communication

Research on JPEC decoding, VGA protocol and getting used to development tools (2-3 weeks).

Another 2-3 weeks for software development .  By week 5 we should have something for prototype 1. 

10 weeks is a possible time to market.

Xilinx XS40 Board: 3.3VDC for FPGA,  5VDC for uC/other components (regulated)

VGA Monitor: 100-240 volts
(Wall power)

Once the JPEG decoder works, there is no need for maintenance, really.  If we wanted a faster decoder, we’d have to use a totally new board, since the XS40 is not upgradable.

Usability can be customized depending on the amount of team members. At the very least, a button can be implemented for picture transitions.  With more people, things such as voice activation or a wireless button can be used.

E5

JPEG Decoder

 

 

 

The board cost $298.00, which includes Triscend Fast Chip software and JTAG download cable
 

Parts:

Black box ~$3

Button ~$1

Wires/Solder ~$1

Protoboard ~$5


VGA Monitor ~$0 (use one from home)

Total: $10

The development board is about 7” x 4”. 

2 People: Feasible

3 People: Definitely feasible, but would require more features

4 People:  Definitely requires more functionality.  With 4, XP can be used to our advantage (2 people on uC part, 2 on FPGA)  

8051/52-compatible microcontroller (10 MIPS at 40MHz).

 

Two channel DMA controller.  Up to 40Mbytes/s transfer rate (1 byte/cycle)

 

128Kbyte Flash Memory.

 

Idle and Power-Down modes of operation.

Easily implement peripherals and software can be moved to custom hardware. Documentations easily attained Tutorials are also available It has a four-pin IEEE 1149.1 JTAG interface for easy board-level testing/debugging RS-232 connector for further serial communication 

Should be similar to the XS40 time to prototype

Should be similar to the XS40 time to market

9 V, 500 mA Transformer for development board

                       

Vcc Min: 3.0 V Max 3.6 V

Supply voltage relative to GND

 

The programmable I/O pins has 3.3 V supply voltage but it can handle up to 5 V input without damaging the E5. 

 

 

Maintainability for this Triscend E5 is sufficient.  The documentation for the Triscend E5 can be easily found and readily available on the internet

Usability can be customized depending on the amount of team members. At the very least, a button can be implemented for picture transitions.  With more people, things such as voice activation or a wireless button can be used

ARM

JPEG Decoder

 

 

Altera’s Excalibur EPXA1 development board

~$1195

Parts:

Black box ~$3

Button ~$1

Wires/Solder ~$1

Protoboard ~$5


VGA Monitor ~$0 (use one from home)

ARM development board

Total: $10

Roughly 8” by 6”

2 People: Feasible

3 People: Definitely feasible, but would require more features

4 People:  Definitely requires more functionality.  With 4, XP can be used to our advantage (2 people on uC part, 2 on FPGA)

 32-bit RISC processor, 1.1MIPS/Mhz, 128 Kbytes dual-port RAM, UART, Timer, Watchdog, two rs-232 ports 8Mbyte flash memory, 32-Mbyte SDRAM on board. Three clock sources, JTAG & trace interfaces,

 

1000 system gates for FPGA

 

200MHz (210 Dhrystone MIPS)

Documentations easily attained Tutorials are also available. Two RS-232 ports for communication

 

Better performance means more capacity for pictures, etc.

If readily available, we could build this system in 10 weeks.

May not be able to Market in time if b/c we would probably have to order this product which would put us behind schedule

900mW

Can find documentation for this product easily on the website

Usability can be customized depending on the amount of team members. At the very least, a button can be implemented for picture transitions.  With more people, things such as voice activation or a wireless button can be used