Project - JPEG Decoder
Interests: Designing Embedded Systems, robotics, video games, movies, basketball
Design Project in Architecture / Embedded Systems
Engineering
Notebook / Log
Author: Miguel A Carrillo
Team members: Renato Jareno, Jerome Pasion, Jectofer Dumpit
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Week 1 |
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Mon, Mar 29 |
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Tue, Mar 30 |
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Wed, Mar 31 |
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Thur, Apr 1 |
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Fri, Apr 2 |
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Sat, Apr 3 |
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Sun, Apr 4 |
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Week 2 |
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Date |
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Mon, Apr 5 |
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Emailed Professor Vahid to try to add the class. He is out of town so I am going to start doing the work anyways. |
Try to find a group to work with |
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Tue, Apr 6 |
1 |
Talked to RJ, Jectorfer, and Jerome and decided to join their group doing jpeg decoding. They Briefed me on what the project entailed. |
Ideas are to have 8051 do JPEG decoding to bitmap transferred to FPGA (don’t know which board yet) which will handle the VGA protocol out to the VGA monitor. |
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Wed, Apr 7 |
4 |
Began doing research on JPEG compression/decompression. Looked into XS40 and Tricend. |
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Thur, Apr 8 |
3 |
Did a Tradeoff analysis: XS40 vs. Tricend E5 Looked for more JPEG stuff |
From personal Use I feel that the XS40 would be easier to work with. |
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Fri, Apr 9 |
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Sat, Apr 10 |
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Sun, Apr 11 |
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Week 3 |
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Mon, Apr 12 |
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Tue, Apr 13 |
6 |
Today I was looking farther into the VGA controller. I spent a lot of time looking into how a VGA monitor works, What a bitmap file contains and How to implement a VGA controller. I found some useful code that I am going to try to get to work. I also wrote my part of the Proposal which is on the VGA controller. |
I hope to have the VGA controller working using Active HDL in the CS labs. |
VGA controller I am currently working on. |
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Wed, Apr 14 |
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Thur, Apr 15 |
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Fri, Apr 16 |
4 |
Today I continued researching the bitmap file. For the code I am using I need pixel data 1 byte: 4 pixels per byte. This is not to good of resolution but it’s a start. I found the following link with info on Pixel Data. |
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Sat, Apr 17 |
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Sun, Apr 18 |
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Week 4 |
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Mon, Apr 19 |
5 |
Today I started coding in VHDL. I figured I could have something working by the end of the week. I am trying to simulate this code. I figured once I understand the code I will have a better understanding of implementing the VGA controller on FPGA. |
I plan to have the code working by the end of this week. Tools: Aldec HDL, using the waveform generator to view output of signals. |
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Tue, Apr 20 |
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Wed, Apr 21 |
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Thur, Apr 22 |
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Fri, Apr 23 |
9 |
Today I decided to take some time and help the guys with jpeg decoder. I put the VGA control program aside until tomorrow. I started off by looking over some code from the openJPEG people. I took their code and decided to compile. I tried to compile the source code under Visual C++ 6.0 but I failed to accomplish. I moved on to looking for some more source code and I came across a website for a book called Compressed Image File Formats by John Miano This website describes the book but it also included a link to some jpeg decoder and encoder C++ source files. I decided to take a look and ended up compiling the program. This program makes use of a lot of source files and was hectic to get to compile under Visual C++ 6.0. After changing some of the source files I accomplished creating an executable and passing in a .jpg image in and getting a .bmp out. We now have a working version of a jpeg decoder. |
To run follow directions:
JpegDecoder.exe [inputfile.jpg] [outputfile.bmp]
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Sat, Apr 24 |
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Sun, Apr 25 |
5 |
Today I spent some time working on the VGA controller code. I put together the following BLOCK DIAGRAM that illustrates what I have so far. I have simulated the VGA controller using a test-bench and waveform generator. I am having some trouble with getting correct output. I know it has something to do with the way I set the control lines to the memory because I skip some values at some point. |
I plan to have the memory control signal problem solved by Monday night. |
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Week 5 |
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Mon, Apr 26 |
4 |
Today I figured out that the enable going from the vgacore to the memory was not being set properly. All that had to be done was invert the signal. I continued to test the code with the test bench and I got it working correctly. The timing according to the specs was off by around 2us but I believe this to be no major problem. |
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Tue, Apr 27 |
2 |
Today I Met with RJ and Jerome to show them how the simulator worked. I ran the code for them and showed them the output waveform and explained to them how everything worked. |
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Wed, Apr 28 |
3 |
Today we presented prototype 1 in class and demonstrated to Greg in the lab. Overall I think it went pretty well. |
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Thur, Apr 29 |
6 |
Today I spent most of the day trying to fully comprehend how jpeg decoding works. To do this I was looking through my partners links and also did some research of my own. I found the these links to be quite helpful. I know have an overall understanding on the encoding decoding process. The details I am still not quite sure. Meeting up with group this sat to help with the decoding. |
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Jpeg theory Encoding steps Encoding process visual Color spaces Australia Jpeg encoder Senir design Nice detailed encoding/decodin process Encoding research paper
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Fri, Apr 30 |
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Sat, May 1 |
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Sun, May 2 |
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Week 6 |
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Mon, May 3 |
4 |
Took some test jpeg files and began to look at the Huffman code tables of each. I m trying to fully understand how the Huffman tables are stored on the jpeg file. |
Having major trouble deciphering the info on jpeg file |
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Tue, May 4 |
3 |
Started looking at implementing a UART in VHDL. We are planning to eliminate the 8051 by using FPGA capabilities. If we implement a UART that can take in data sent from the PDA then we no longer need the 8051 since jpeg decoding is being done of PDA. |
Using Xilinx software in EE labs having some trouble compiling. I will continue working on this later in the CS labs. |
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Wed, May 5 |
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Thur, May 6 |
5 |
I continued working with the Huffman decoding. I had a chance to talk to Ryan during class on wed and he clarified some stuff for me. After my talk with Ryan I had a clear understanding on how jpeg stored the Huff tables. So today I continued with that. I used hexdump on vahid.jpg The picture that Dr. Vahid had on his site and I took apart all the Huff tables from the dump. I then proceeded to modify some of the code from JpegDecoder.exe and was able to extract the huff decoding part and make it work on the files I had created. This proved to be a big step as I have spent a lot of time trying to decipher this. Next step is to Scan through the data and actually use the huff table to decode into bmp data. |
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Fri, May 7 |
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Sat, May 8 |
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Sun, May 9 |
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Week 7 |
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Mon, May 10 |
4 |
Started working with the XS40 board. I started using the Xilinx Foundation Series software at Surge 173 but apparently there was something wrong with the software. When I tried to synthesize my code a warning message would come on and would not let me continue. So I just proceeded to study the XS40 board looking at how the pins were configured and how we could map pins to a bigger SRAM. |
The SRAM on XS40 board is 32Kbytes we are going to need at least around 300Kbytes to support 1 image. We decided we can map pins on XS40 board to an external memory chip. |
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Tue, May 11 |
4 |
Today I tried using the software at Bourns 252, I think this is CS120a labs. The lab is set up with XS95 boards. They use the same Xilinx software. I proceeded to run lab 2a from CS120B website which basically makes the 7-seg led on board go from 0-F. Simple code. I downloaded code and synthesized perfectly. Then I downloaded on the XS40 board and it worked. After completing some more labs I started working on the VGA vhdl code. I was having some trouble with the implementation part because warnings came up with the netlist. |
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Wed, May 12 |
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Thur, May 13 |
8 |
Today I continued working with VGA code and I successfully got it to synthesize and created the bit file. The code reads pixels out from the 32K SRAM on the board so I had to download a .hex file onto the board. I created a template.hex file just to print out some color pixels. I downloaded the bitfile and hex file and proceeded to test. I connected a VGA monitor and the pixels were printed out onto the screen. J The next thing to do is figure out how I can modify bmp file to output to VGA monitor trough the code. |
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Fri, May 14 |
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Sat, May 15 |
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Sun, May 16 |
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Week 8 |
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Mon, May 17 |
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Tue, May 18 |
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Wed, May 19 |
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Thur, May 20 |
7 |
Worked with RJ to accomplish VGA design. We were implementing a structure that will allow us to with data into the SRAM. We had a problem when we tied to map out components. Since we had a component that wrote to SRAM and a VGA component that read from SRAM, we had a problem with sharing the wires to the VGA. |
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Fri, May 21 |
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Sat, May 22 |
6 |
Today we worked more closely with the VGA architecture and we decided we were going about it all wrong. We were trying to implement a structure that was not reasonable. We changed out design completely. |
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Sun, May 23 |
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Week 9 |
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Mon, May 24 |
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Tue, May 25 |
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Wed, May 26 |
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Thur, May 27 |
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Fri, May 28 |
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Sat, May 29 |
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Sun, May 30 |
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Week 10 |
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Mon, May 31 |
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Tue, June 1 |
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Wed, June 2 |
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Thur, June 3 |
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Fri, June 4 |
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Sat, June 5 |
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Sun, June 6 |
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Last
Updated: 04/01/04