Scale Length Theory of MOSFETs
By
Dr. Yuan Taur
Department of Electrical and Computer Engineering
University of California, San Diego
When: Tuesday, May 26, 2009
Time: 2:00pm - 3:00pm
Location: A265 Bourns Hall
Abstract:
This talk reviews the recent development of scale length theory of MOSFETs. For any given technology node, CMOS performance is limited by the shortest channel length that can be made while maintaining robust 2-D electrostatic integrity. In the initial one-region scale length model for uniformly doped bulk MOSFETs, only the vertical field at the silicon-oxide interface is considered. The important role of the backgate is made clear through the requirement of the depletion layer depth. Later on, two-region scale length model is developed by taking both the vertical and the lateral fields into account to deal with MOSFETs with relatively thick, high- gate dielectrics. The scale length theory is extendable to three or more regions of different dielectrics. It gives useful guidelines that, with quantum mechanical considerations, allow the projection of scaling limits for bulk, SOI, double-gate, and nanowire MOSFETs.
About the Speaker:
Yuan Taur received the Ph.D. degree in physics from University of California, Berkeley. From 1981 to 2001, he was a Research Staff Member with IBM Thomas J. Watson Research Center, Yorktown Heights, New York. Since October 2001, he is professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Taur is elected a Fellow of the IEEE in 1998. He is currently the Editor-in-Chief of IEEE Electron Device Letters, and Program Chairman of 2002 Symposium on VLSI Technology. Dr. Taur's current research interest is in advanced CMOS devices and their scaling limits. He co-authored a book, "Fundamentals of Modern VLSI Devices," published in 1998.