University of California, Riverside

Department of Electrical and Computer Engineering



NSF supports Prof. Tan's research for parallel simulation of large VLSI systems on many-core microprocessors


NSF supports Prof. Tan's research for parallel simulation of large VLSI systems....
 

Professor Sheldon TanEE Professor Sheldon Tan (PI) received three –year grant  from National Science Foundation for exploring new techniques for parallel simulation and analysis of VLSI systems on many-core microprocessors.   The NSF project  is titled “SHF:Small:GPU-Based Many-Core Parallel Simulation of Interconnect and High-Frequency Circuits” with 270K for three years.

Parallel computing based on the general purpose Graphic Processing Unit (GPU) provide massive many-core parallelism and can deliver staggering performance improvements over traditional single-core and existing general multi-core computing techniques. The recent introduction of general-purpose GPU (GPGPU) has gained strong interests from the scientific community to tackle many computationally intensive problems. In this project, Prof. Tan’s team will investigate parallel computing algorithms for simulation and analysis of large scale integrated circuits and systems, which are challenging task for today’s chip designers.  This research seeks to investigate new parallel simulation approaches to solving massive interconnect circuits and analog/RF/MM integrated circuits based on single node general GPU or networked GPUs on a computer (GPU-cluster).

Prof. Tan’s team will investigate new parallel simulation algorithms based on analytic solution for structured interconnect circuits like on-chip power delivery and clock distribution networks. They will also develop new parallel shooting-Newton methods for high-frequency circuits (such as radio frequency and millimeter circuits). The new method will explore structured Krylov-subspace, and GPU-based parallelization to improve efficiency as well as the convergence of RF/MM integrated circuit simulation.

Prof. Tan’s team will work with the industry partner to bring immediate impacts on the design community to improve the design productivity for nanometer VLSI systems.

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