University of California, Riverside

Department of Electrical and Computer Engineering



NSF funds Dr. Sheldon Tan's Industrial Collaboration on Parallel Analysis of VLSI Circuits


NSF funds Dr. Sheldon Tan's Industrial Collaboration on Parallel Analysis of....
 

Professor TanProf. Sheldon Tan's group is collaborating with Cadence Design Systems Inc. (www.cadence.com <http://www.cadence.com>) in investigating efficient analysis solutions based on multi-core computing technologies.  The leap from single-core to multi-core technology (also called chip multiprocessing, CMP) has permanently altered the course of computing.

CMP enables increased productivity, powerful energy-efficient performance, and breakthrough in parallel computing capability and scalability. The project will leverage the emerging threading-based parallel computing from CMP for efficient design of VLSI chips. Dr. Tan's MSLAB will work closely with Cadence Virtuoso Custom Design research and development (R&D) team to jointly investigate and develop highly scalable parallel simulation algorithms based on the multi-core platforms for analysis of nanometer analog/mixed-signal circuits with massive parasitic interconnects.

The two-year program was funded by National Science Foundation GOALI (Grant Opportunities for Academic Liaison with Industry ) program. The program will provide funding supports for US graduate students to work closely with Cadence Design Systems Inc.

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University of California, Riverside
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Electrical and Computer Engineering
Suite 343 Winston Chung Hall
University of California, Riverside
Riverside, CA 92521-0429

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