University of California, Riverside

Department of Electrical and Computer Engineering

Li Wang - A Talk on "Whole-chip ESD CAD Tool Design and ScalableESD Device Modeling Methodology"

Li Wang - A Talk on "Whole-chip ESD CAD Tool Design and ScalableESD Device Modeling....

Li Wang - A Talk on "Whole-chip ESD CAD Tool Design and ScalableESD Device Modeling Methodology"

June 5, 2015 - 10:00 am
Winston Chung Hall, 202

Electrostatic discharge (ESD) failure is a major reliability problem to integrated circuits (IC). On-chip ESD protection is mandatory for all IC chips to protect against any possible ESD damages. Therefore, Whole-chip ESD protection circuit simulation is essential to chip-level ESD protection design synthesis, optimization, verification and prediction. Today, trial-and-error approaches still dominate in practical ESD circuit designs due to lack of full-chip ESD simulation tools and accurate ESD device modeling technique.

This thesis proposed a new chip-level ESD CAD tool, which extracts ESD devices from layout files, generates ESD netlist, simulates ESD discharge function on chip level and conducts full-chip ESD zapping test by simulation. This CAD tool is designed with several unique algorithms and a smart ESD parametric checking mechanism, which takes full consideration of ESD protection operation principles. Therefore, this CAD tool is different from existing simple ESD spacing and bus resistance checking approaches, and can achieve whole-chip ESD protection verification and prediction. The CAD tool consists of three modules: ESD Extractor, ESD Inspector and ESD Zapper. ESD Extractor is a new function to extract arbitrary ESD structures at full chip level. Decomposed-based subgraph isomorphism algorithm is invented for ESD devices extraction to improve time efficiency. ESD Inspector is to remove non-critical ESD devices extracted based upon a novel smart parametric checking mechanism. In addition, ESD Zapper is developed to perform ESD protection zapping test simulation by implementing Dijkstra's algorithm to resolve the problem of finding the critical ESD discharging path. Last but not the least, full chip ESD protection was designed and verified the CAD tool implemented in 0.35µm BiCMOS technology.

Among all the ESD device models reported for traditional diode and MOSFET type ESD structures, due to complex ESD behaviors, particularly the electro-thermal-process-device-circuit-layout coupling effects, existing ESD models have limited accuracy in describing complex ESD physics, such as thermal boundary condition and snapback I-V behavior.

In this thesis a new scalable ESD behavioral modeling technique is presented, which uses Verilog-A to develop accurate ESD behavior models for novel nano crossbar ESD protection structures, novel 3D field-programmable ESD protection structures including SONOS and NCD ESD devices, silicon controlled rectifier (SCR) based ESD protection structures, HV diode and SCR ESD protection structures, 28nm CMOS gated diode and DTSCR ESD protection structures. The new ESD behavior modeling technique was fully verified by SPICE circuit simulation and TLP testing, which will enable whole-chip ESD circuit design optimization and verification.

Flip chip technique using ball grid ball (BGA) pad-ring arrays is a popular technology for small footprint chips used in size-sensitive electronics. However, ESD protection design for ICs using large BGA pad-ring array is an emerging challenge since where to place an ESD structure becomes a real layout design headache.

In this thesis, a BGA pad-ring array with different ESD metal routing for a VLC transceiver implemented in 180nm BCD technology was verified at whole-chip level. The ESD structures and their ESD-critical parameters, and the ESD metal bus resistance were extracted by our ESD Extractor CAD tool. The new ESD behavior modeling technique was used to model the ESD structures. The extraction and modeling was validated by SPICE simulation and TLP testing for different ESD metal routing.



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University of California, Riverside
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Electrical and Computer Engineering
Suite 343 Winston Chung Hall
University of California, Riverside
Riverside, CA 92521-0429

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