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Ph.D. Defense Tuesday, November 28, 2006 Bourns Hall A265 11:00am Title: Automatic Generation from C to VHDL for Reconfigurable Devices Abstract: The logic capacity of reconfigurable devices has been increased drastically in the past ten years. However, the design productivity is increasing at a lower pace. It is desirable to have a higher level of abstraction to bridge this design productivity gap. This will allow us to make the most of the abundant logic resources on our devices with a shorter design time and at a lower labor cost. This work has built a compiler that takes C code as input and generates synthesizable VHDL code targeting reconfigurable devices. This work has created our execution model and an intermediate representation of the compiler. This intermediate representation supports concurrency as well as the instantiation of and accesses to on-chip storage structures. The compiler has an input data reuse approach that relieves the memory bandwidth pressure. The compiler generates a buffer, called smart buffer, in VHDL, to store and reuse the fetched data elements from the input data stream. The compiler exploits both the loop-level and the instruction-level parallelism when generating data-path. Predication is used to schedule the action of data-path and to handshake with buffers. The compiler wraps IP cores so they can be controlled by the same predication mechanism as the reminder of the data-path. |
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