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Ph.D. Defense Tuesday, March 13, 2007 Bourns Hall – A171 1:00PM Title: Engineering the Nanocrystal Floating Gates for Nonvolatile Flash Memory Devices Abstract: Conventional semiconductor nonvolatile flash memory is encountering serious issues in further scaling. A compromise has to be made so that we can achieve either faster programming/erasing but with shorter retention, or slower programming/erasing but with improved retention. Currently proposed Si and metal nanocrystal memories can solve this issue, but bring their owns: retention of Si nanocrystal memory varies with the annealing history and metal nanocrystals will react with tunnel oxide. In this work, we demonstrated theoretically that with Ge/Si or Si/SiC0.008 hetero-nanocrystals, memory retention can be dramatically improved while the programming/erasing performance remain almost the same as those of Si nanocrystal memory. Further, with simulations and experimental results as well, we demonstrated that TiSi2/Si hetero-nanocrystals memory devices (both MOS and MOSFET devices) have greatly prolonged retention as well as significantly faster programming/erasing speeds, and similar endurance characteristics, as compared to the Si nanocrystal reference device. The dual-bit function was also successfully realized on this TiSi2/Si hetero-nanocrystals memory. The technique used for TiSi2/Si hetero-nanocrystal fabrication is the well-known two-step self-aligned silicidation, which is a standard process in semiconductor industry. Therefore, the process used in our works is completely compatible to existing Si process line. It is concluded that hetero-nanocrystal can replace Si or metal nanocrystals for future generation nonvolatile flash memory devices, with superior programming/erasing and retention performances. |
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