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Prof. Sheldon Tan Department of Electrical Engineering University of California at Riverside on Monday, October 22, 2007 11:00 am – 12:00 pm, A265 Bourns Hall Abstract: The talk consists two parts. The first part is about the novel approach for behavioral thermal modeling for multi-core microprocessors and the second part is about designing thermal and reliability efficient caches. With aggressive scaling, thermal and power issues have has been recognized as a principal challenge in ITRS Roadmap for designing current and future high-performance microprocessors. I first present novel thermal modeling techniques at the chip architecture level for potential run-time dynamic thermal management and designing more efficient temperature efficient VLSI microprocessors. The new techniques are based the pencil of function techniques to capture the transfer functions of architecture-level thermal systems. It is a very general modeling approach as it captures the transient thermal responses at behavioral level in “black-box” style. Experimental results on Intel’s Quad-Core microprocessor demonstrate the effectiveness of the proposed method. Secondly, we study the impact of process variations, particular the gate length variation, on the temperature and reliability of on-chip caches. Process variability is one of grand challenges in design nanometer VLSI integrated system. Our statistical simulation shows that, under process variation, 85% of the caches see shortened lifetime, with average lifetime being 81.6% of the ideal cache. This paper proposed a dynamic cache subarary permutation scheme to improve the reliability of the caches. Experiments show that our scheme can extend the cache lifetime by up to 20.3% and reduce the peak temperature by 7 degrees on average. About the Speaker: Dr. Tan is an Associate Professor in the Department of Electrical Engineering, University of California at Riverside. He received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999. Dr. Tan is the recipient of NSF CAREER Award in 2005. Dr. Tan received a Best Paper Award from IEEE International Conference on Computer Design (ICCD’07), Best Paper Award Nomination from 2005 IEEE/ACM Design Automation Conference, Best Paper Award from 1999 IEEE/ACM Design Automation Conference. He also co-authored book Symbolic Analysis and Reduction of VLSI Circuits by Springer/Kluwer 2005 and Advanced Model Order Reduction Techniques for VLSI Designs, by Cambridge University Press 2007. |
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